In recent years, there have been remarkable advancements in semiconductor processes. The size of semiconductor integrated circuits is being reduced yearly, bringing a reduction in the size of semiconductor chips as well.
As the size of semiconductor chips is reduced, the number manufactured per wafer increases, and yields also tend to rise, allowing for a steady decline in cost.
On the other hand, pads used for external connection during testing and assembly must be included on the surface of a semiconductor chip. Given that there are individual constraints on the sizes and disposition of the pads during testing and assembly, the size of the pad disposition area has not currently been reduced very much.
Consequently, the percentage of the entire area of semiconductor chips which the pad disposition area occupies increases yearly and is an obstacle to the reduction in size of semiconductor chips.
With high-performance multi-pin semiconductor chips in particular, a pad constraint occurs whereby a chip's size is determined solely by the disposition of the pads, regardless of the circuit dimensions of the semiconductor integrated circuit. However remarkable the improvements in semiconductor processing may be, a significant reduction in the dimensions of multi-pin semiconductor chips cannot be expected as long as the dimensions of the pad disposition area are not reduced.
A method that prevents the size of the semiconductor chip from being affected by the size of the pad disposition area is disclosed in patent document 1 whereby pads are disposed above a given circuit device formation area.
Since the pads are disposed on the functional devices in the method in patent document 1, stress from probe pressure, etc. is applied on the interface beneath the pad during wafer testing, with the functional devices beneath the pads becoming more susceptible to damage as the miniaturization of semiconductor processing advances. A serious problem thus resides in the method of patent document 1 in terms of reliability.
In view of this, damage due to stress is avoided in patent document 1 by adequately increasing the pad thickness to 15000 Å and lowering the pressure of the probe from the conventional 10 g/pin to 5 g/pin.
Patent document 1: Japanese Patent Application Publication No. 11-307601 (p. 5, FIG. 1)